lecture slides, pictures, and attendees' page
3rd edition of the International Seminar on Application-Specific Multi-Processor SoC
7 - 11 July 2003, Hotel Alpina, Chamonix, France
by Ahmed A. Jerraya, TIMA Laboratory,
Grenoble, France & Wayne H. Wolf, Princeton
University, Princeton, USA
In co-operation with EDAA and IEEE Circuits and Systems Society, and sponsored by IST in the frame of IST project REASON (IST - 2000 - 30193)
Modern System-on-Chip (SoC) design shows a clear trend towards integration of multiple processor cores on a single chip. Typical multi-processor SoC applications like network processors, multimedia hubs and base-band telecom circuits have particularly tight time-to-market and performance constraints which require a very efficient design cycle. The trend is then to build large SoCs as a set of programmable and specific HW components interconnected through a sophisticated on-chip network. This evolution is creating several breaking points in the design process. Current RTL design methods and existing designers are hard to scale to accommodate these complex systems. The main idea of this seminar is to gather key R&D people from the different domains required to master this new kind of systems.
The seminar will bring together more than 30 world class R&D speakers from academia and industry to discuss fundamental and strategic issues to master multi-processor SoC design. The seminar will be made of:
- An introduction day made of tutorials on basics for SoC design ;
- 3 days to present state-of-the art research related to SoC. Senior speakers in key areas of SoC design will present their work and experiences ;
- An executive half day session bringing together managers from key industries related to SoC to discuss challenges and opportunities for future SoC applications & technologies.