For further information, please contact the General chair: Pierre-Emmanuel Gaillardon
TIMA Lab - Grenoble University, France
Acceleration of software simulation in dynamic binary translation
During dynamic binary translation, target memory accesses need to undergo virtual target to virtual host address translation. This is done using helpers, functions that traverse complex data structures to perform that translation as quickly as possible. Calling helpers is a time consuming process and it greatly impacts the performance of dynamic binary translation. In this talk, we propose to translate a target load/store instruction into a host load/store instruction which, when reach the first time, will lead to a page fault. By installing a specific page fault handler, we modify the host page table so that the following target memory accesses directly hit host memory that models the content of the target memory.
Frederic Petrot received the PhD degree in Computer Science from Universite Pierre et Marie Curie (Paris VI), Paris, France, in 1994, where has been Assistant Professor in Computer Science until September 2004. From 1989 to 1996, F. Petrot was one of the main contributors of the open source Alliance VLSI CAD system, and from 1996 to 2004, he led a team focusing on the specification, simulation and implementation of multiprocessor SoCs. He joined TIMA in September 2004, where he holds a professor position at Grenoble Institute of Technology, France. Since 2006, he heads the System Level Synthesis group of TIMA. His research interests are in multiprocessor systems on chip architectures, including circuits and software aspects, and CAD tools for the design and evaluation of hardware/software systems.