17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
For further information, please send email to Frédéric Pétrot
Tokyo Institute of Technology, Japan
Cryptographic ASIP Designs using C2RTL Framework
In this talk, we introduce our C-based ASIP design framework (C2RTL) targeted for AES and RSA cryptography functions. In both cases, C algorithms are first profiled on our baseline 4-stage RISC processor C model, then the core cryptographic C models are directly ported into the processors as HW engines and custom instructions. In AES-ASIP, a single round of AddKey/SubByte/ShiftRow/MixColumn functions are merged into a single custom instruction, resulting in a speedup of 3700x. In RSA-ASIP, several custom instructions for driving the 2048-bit Montgomery multiplication are implemented, resulting in a speedup of 140x.
Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Global Scientific Information and Computing Center. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.