17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
For further information, please send email to Frédéric Pétrot
Konica Minolta, Japan
Designing structure of image processing in MFP
Hardware architecture that is employed on MFP controller is realized by integrating 3 function blocks; 1. Controlling function using ARM core that is applied to devices such as Smartphone, 2. Memory controlling function that inputs, deliveries, prints and storages image, 3. Imaging processing function that corrects, edits and converts imaging data, and then making SoC.
When thinking of employment technology of system controlling function, how fast you can acquire and use leading-edge technology is an important R&D requirement. However, since it has generic architecture following technology trend of semiconductor as its base, there is no technology difference between companies, and so the commoditization is in progress. Also, looking at memory controlling function, architecture itself has the same function with generic data bus technology represented by PCI-Express even image data compression and decompression technology differ from company to company.
On the other hand, looking at imaging processing function, each company develops unique algorithm from the early stage of MFP digitizing to make a hardware as a design asset to improve its performance and function. This hardware asset is a combined structure of controlling functions of large-sized and divided local memory group and pipe-line following image processing flow, and the structure can be looked very unique when looking from other industries.
In this report, we are focusing on the imaging processing in MFP and explaining the background of our R&D and future direction from a viewpoint of ASIC design.
・Gate size of ASIC/SoC development, change of memory capacity
・Basic block and image flow of image processing
・Method of using memory in image processing function
・Future direction of image processing function